3 ms·
Seems similar to the Chisel compiler for RISC-V: https://github.com/chipsalliance/chisel3 https://github.com/chipsalliance/chisel3
by spullara 5y ago
Seems similar to the Chisel compiler for RISC-V:
https://github.com/chipsalliance/chisel3 https://github.com/chipsalliance/chisel3
- logane 5y agoChisel and this project are different; chisel is a programming language to design hardware while this is a build tool for hardware design. In software we have a nice compilation process that transforms code into machine code. However, to "compile" an ASIC you go from a hardware description language like verilog (which basically describes the design) and pass it through a complicated pipeline that composes a number of different tools. Right now, engineers use ad-hoc flows that use bash/TCL to glue together all the parts --- the project posted above is an attempt to cleanly specify + control the "compilation" process.
- gsmi 5y agoI don't think it's either. I am pretty sure it is a competitor to OpenRoad. https://theopenroadproject.org https://theopenroadproject.org
- adapteva 5y agoNo, it it is not a competetitor to openroad. It's more like a build system, like how make sits on top of llvm. Openroad is one of the tools under the hood.