9 ms·

Does this factor in memory access and so on? Or is it scoped to tight numeric computing?

• vlovich123 5y ago
  It's not scoped to anything. Think of it like assembly. If you understand your problem domain at a sufficiently deep level, you can design a more optimal architecture. For example, Google TPUs don't just have fast-paths for numeric computing. They change the memory layout & chip communication architecture to optimize for ML workloads so that your chip is constantly fed with data and not bottlenecked on memory access or cross-chip communication (in addition to direct dedicated access to a large memory that stores your data set which requires synchronization with system RAM and cross-chip cache invalidation, there's dedicated on-chip memory that's usable as scratch/storing a part of the data set that doesn't need any of that). There are of course potentially problems that aren't made meaningfully faster by going to ASIC just as there are problems where going from ASM to C++ or C++ to JS don't benefit. However, typically any problems that are hitting some kind of performance bottleneck could benefit & then it just becomes a matter of cost vs reward.