OpenRISC, which I worked on in an embedded application, also has branch delay slots. I thought it looked like a clever idea. Then I wondered why RISC-V so quick

OpenRISC, which I worked on in an embedded application, also has branch delay slots. I thought it looked like a clever idea. Then I wondered why RISC-V so quickly took over OpenRISC as the darling ISA of the open source community. What I read then is that branch delay slots was one of the problems, as it creates problems when designing fast modern (superscalar) CPUs. That’s been my impression of RISC-V in general. Whenever someone thinks another ISA does it better, there seems to be a very well thought-out reason for RISC-V’s decision, when you take into consideration that it’s built to scale from the smallest microcontroller to the biggest CPU. The RISC-V standards is also evolving, if something isn’t there it can also be that it’s planned for future revisions. There’s a proposed revision coming up that would make RISC-V beat ARM in code density across the board, on real world embedded code.