I mean, it doesn't have any microcode, and does better than MIPS ironically at achieving the whole "Microprocessor without Interlocked Pipelined Stages" thing b

I mean, it doesn't have any microcode, and does better than MIPS ironically at achieving the whole "Microprocessor without Interlocked Pipelined Stages" thing because of directly exposing the divide pipeline in single cycle units. Having to add pipeline interlocking from the EX stage just for that as well as the microcode itself would have been non trivial from a gate count perspective on a core that's already cutting gates left and right. And it's neat to be able to choose the divide precision you need down to the cycle. I agree though in the general case, hence why I end with it being a little ascetic these days.