3 ms·

Branch delay slots make. assembly weird

• ithkuil 5y ago
  Go away NOP!
• wyldfire 5y ago
  llvm has a cool tool to statically evaluate your code on a model scheduler [1]. Not sure how many backends are supported beyond x86, but it looks pretty handy. [1] https://llvm.org/docs/CommandGuide/llvm-mca.html https://llvm.org/docs/CommandGuide/llvm-mca.html
  • mhh__ 5y ago
    Non-x86 architectures are vaguely supported, however the key thing here is that it needs a scheduler model i.e. architecture isn't enough. I think the basics of in-order target support is being worked on (possibly merged, haven't been keeping up to date) https://reviews.llvm.org/D94928 https://reviews.llvm.org/D94928 Other tools to do this exist (or have existed, Intel IACA rest in peace), but I'm slightly sceptical how useful they are in practice. They can't model anything transient in the processor (can't easily, at least) like branch prediction and the memory hierarchy. That and there's only so much detail one can fit inside a model.