Branch delay slots are pretty common on old-school RISC archs such as MIPS and SPARC, but AFAIU when those designs were faced with microarchitectural evolution

Branch delay slots are pretty common on old-school RISC archs such as MIPS and SPARC, but AFAIU when those designs were faced with microarchitectural evolution the initial simplicity turned out not to be worth it. Neither PowerPC, Alpha, ARM (if you consider it a RISC), nor RISC-V have them. (A similar thing happened with ARM’s two-words-ahead PC.) It’s another matter if your microarchitecture is your architecture: apparently modern DSPs still have them, although I don’t know where you could learn about those, what with most designs being secret.