3 ms·

A cool thing about Thumb/ARM, is that you can actually switch between the two instruction sets in your binary. You essentially dump your cache when this happens

A cool thing about Thumb/ARM, is that you can actually switch between the two instruction sets in your binary. You essentially dump your cache when this happens, but you can do it.

mananaysiempre 5y ago
... Except on ARM micros, where Thumb probably matters most nowadays, because Cortex-M only runs in Thumb mode.
- duskwuff 5y ago
  And not on ARM64, which has no Thumb equivalent.
  - mananaysiempre 5y ago
    Well yeah, but “only runs ARM” is less surprising to me than “only runs Thumb”, especially on 64-bit where it’s essentially a different architecture altogether. Or maybe I’m just crabby because I wanted to write a Thumb-2 assembler, took a long look at the instruction encoding and gave up.
  - Symmetry 5y ago
    Which makes sense. If you want 64 bit pointers you probably don't have so little memory that you're looking to compress your binaries.
- pm215 5y ago
  Extremely nerdy sub-detail -- M-profile actually has all the handling for the Thumb-to-Arm switch architecturally, with the LSB of a branch target being significant and a T bit in the PSR to tell you what mode you're in, which you can set to 0. It's just that attempting to actually execute an insn with PSR.T==0 will trigger a UsageFault :-) (The CPU is even required to fetch the insn from memory first -- a MPU fault will take precedence over the T-bit-clear fault.)
pm215 5y ago
Why would a thumb/arm switch invalidate the caches? It's just an interworking branch, it isn't even a context switch.
danachow 5y ago
> You essentially dump your cache when this happens, but you can do it. Never heard of this and it makes no sense. The cache is pretty decoupled from the CPU pipeline. I saw a similar comment from someone discussion RISC-V mentioning that ARM/Thumb interworking is costly. I have no idea where these myths come from - really bizarre.

3 ms·

A cool thing about Thumb/ARM, is that you can actually switch between the two instruction sets in your binary. You essentially dump your cache when this happens

by tylerflick 5y ago

A cool thing about Thumb/ARM, is that you can actually switch between the two instruction sets in your binary. You essentially dump your cache when this happens, but you can do it.

mananaysiempre 5y ago
... Except on ARM micros, where Thumb probably matters most nowadays, because Cortex-M only runs in Thumb mode.
- duskwuff 5y ago
  And not on ARM64, which has no Thumb equivalent.
  - mananaysiempre 5y ago
    Well yeah, but “only runs ARM” is less surprising to me than “only runs Thumb”, especially on 64-bit where it’s essentially a different architecture altogether. Or maybe I’m just crabby because I wanted to write a Thumb-2 assembler, took a long look at the instruction encoding and gave up.
  - Symmetry 5y ago
    Which makes sense. If you want 64 bit pointers you probably don't have so little memory that you're looking to compress your binaries.
- pm215 5y ago
  Extremely nerdy sub-detail -- M-profile actually has all the handling for the Thumb-to-Arm switch architecturally, with the LSB of a branch target being significant and a T bit in the PSR to tell you what mode you're in, which you can set to 0. It's just that attempting to actually execute an insn with PSR.T==0 will trigger a UsageFault :-) (The CPU is even required to fetch the insn from memory first -- a MPU fault will take precedence over the T-bit-clear fault.)
pm215 5y ago
Why would a thumb/arm switch invalidate the caches? It's just an interworking branch, it isn't even a context switch.
danachow 5y ago
> You essentially dump your cache when this happens, but you can do it. Never heard of this and it makes no sense. The cache is pretty decoupled from the CPU pipeline. I saw a similar comment from someone discussion RISC-V mentioning that ARM/Thumb interworking is costly. I have no idea where these myths come from - really bizarre.