2 ms·

BitGrid – Brilliant, or Waste of Time?

peter_d_sherman 5y ago
HN user mikewarrot writes the following, in the following two articles/posts: https://news.ycombinator.com/item?id=27230989 https://news.ycombinator.com/item?id=27230989 >"I've had a chip design bouncing around in my head since the 1980s, now I can finally get it made. Thanks so much for posting this. The idea is simple... a grid of 4x4 LUTs, each geographic neighbor has 1 bit in, and 1 bit out, there are 16 states, each with 4 outputs. Turns out that this route-less FPGA can do some fairly amazing things, at least in theory. Now I intend to find out. The really old blog I had about it - https://bitgrid.blogspot.com/ https://bitgrid.blogspot.com/" And (as a sub-level reply in the following article): https://news.ycombinator.com/item?id=29417927 https://news.ycombinator.com/item?id=29417927 >"I believe it is possible to have a computing fabric that is so simple there isn't anywhere to hide bugs in it, yet extremely performant. The downside is it wastes transistors, and isn't a Von-Neuman architecture at all. It's a grid of 4 in, 4 out look up tables (that's 64 bits of state each), each exchanging 1 bit with its cartesian neighbors, clocked in alternate phases like a chess board to prevent all race conditions. It's Turing complete, can route around bad cells, and you could securely partition a program to run in part of it, but not all. I wrote a bunch of blog posts on this theoretic hardware a while ago http://bitgrid.blogspot.com http://bitgrid.blogspot.com" PDS: I think this is an absolutely brilliant idea, if it works! mikewarrot, if you're listening, I'd love to know more! And I think the HN community would love to as well! Were you ever able to successfully make one of these?
- csense 5y ago
  In another blog post from 2008 he seems to say that FPGA uses way too much on interconnects, some other technology called HRSA realizes the problem, BitGrid takes it to an extreme [1]. So you can build simple circuits like muxes and latches. What about complex circuits like adders or registers? Could you build a CPU with a BitGrid, or do you run into problems (e.g. topological issues because the clock needs to be routed everywhere)? The real thing for further progress is some kind of compiler that can automatically take a design in an HDL (possibly a subset of an existing HDL or a custom HDL if supporting one of the popular HDL's in full is too ambitious). That would let you simulate complex designs and study whether topological issues or other fundamental problems arise in practical designs, work out approaches for dealing with them, measure how much penalty you pay, and see whether you can really get by without interconnects. Just some random thoughts, I'm not really a hardware guy. Hope mikewarrot shows up here, would be fascinating to get some updates and maybe ask a few questions :) [1] https://bitgrid.blogspot.com/2008/07/hrsa-close-but-no-cigar.html https://bitgrid.blogspot.com/2008/07/hrsa-close-but-no-cigar...

HN user mikewarrot writes the following, in the following two articles/posts: https://news.ycombinator.com/item?id=27230989 https://news.ycombinator.com/item?id=27230989 >"I've had a chip design bouncing around in my head since the 1980s, now I can finally get it made. Thanks so much for posting this. The idea is simple... a grid of 4x4 LUTs, each geographic neighbor has 1 bit in, and 1 bit out, there are 16 states, each with 4 outputs. Turns out that this route-less FPGA can do some fairly amazing things, at least in theory. Now I intend to find out. The really old blog I had about it - https://bitgrid.blogspot.com/ https://bitgrid.blogspot.com/" And (as a sub-level reply in the following article): https://news.ycombinator.com/item?id=29417927 https://news.ycombinator.com/item?id=29417927 >"I believe it is possible to have a computing fabric that is so simple there isn't anywhere to hide bugs in it, yet extremely performant. The downside is it wastes transistors, and isn't a Von-Neuman architecture at all. It's a grid of 4 in, 4 out look up tables (that's 64 bits of state each), each exchanging 1 bit with its cartesian neighbors, clocked in alternate phases like a chess board to prevent all race conditions. It's Turing complete, can route around bad cells, and you could securely partition a program to run in part of it, but not all. I wrote a bunch of blog posts on this theoretic hardware a while ago http://bitgrid.blogspot.com http://bitgrid.blogspot.com" PDS: I think this is an absolutely brilliant idea, if it works! mikewarrot, if you're listening, I'd love to know more! And I think the HN community would love to as well! Were you ever able to successfully make one of these?

csense 5y ago
In another blog post from 2008 he seems to say that FPGA uses way too much on interconnects, some other technology called HRSA realizes the problem, BitGrid takes it to an extreme [1]. So you can build simple circuits like muxes and latches. What about complex circuits like adders or registers? Could you build a CPU with a BitGrid, or do you run into problems (e.g. topological issues because the clock needs to be routed everywhere)? The real thing for further progress is some kind of compiler that can automatically take a design in an HDL (possibly a subset of an existing HDL or a custom HDL if supporting one of the popular HDL's in full is too ambitious). That would let you simulate complex designs and study whether topological issues or other fundamental problems arise in practical designs, work out approaches for dealing with them, measure how much penalty you pay, and see whether you can really get by without interconnects. Just some random thoughts, I'm not really a hardware guy. Hope mikewarrot shows up here, would be fascinating to get some updates and maybe ask a few questions :) [1] https://bitgrid.blogspot.com/2008/07/hrsa-close-but-no-cigar.html https://bitgrid.blogspot.com/2008/07/hrsa-close-but-no-cigar...