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Apple M1 Max die has an entire hidden section on the bottom
- robbiep 5y agoSubtitled: Person tweets rumour with zero evidence and becomes runaway tweet storm - oh wait, that isn’t what happened
- baybal2 5y agoLooks like a provision for some kind of EMIB like interconnect.
- ksec 5y agoThis is the first time someone at least make some sense of the whole M1 Max Chiplet theory / hypothesis. That there is an interconnect ready. Unlike all previous comments there people suggest they magically stack 2 - 4 SoC together. The TSMC MCM interposer size is the same as 4x M1 Max Die Size. Should they choose that route at a potential of 500W+ TDP Design. Still doesn't solve NUMA issue though. Along with GPU access. This is basically the same design as Zen 1. It was the whole reason why there is an IOD in the middle with Zen 2 and above. And I hope Apple has something clever to show the word why Zen 1 failed and they succeed. On the GPU I am thinking something from PowerVR [1] if it works as advertise. I just wish we could get more information soon. [1] https://www.anandtech.com/print/16155/imagination-announces-bseries-gpu-ip-scaling-up-with-multigpu https://www.anandtech.com/print/16155/imagination-announces-...
- shituonui 5y agoIn what universe did Zen 1 fail? Zen 1 was one of the best-performing designs in the world and scaled very well to high core counts. The fact that Zen 2 is better doesn't reduce the excellence of Zen 1.
- ksec 5y ago>In what universe did Zen 1 fail? Failed in the context of NUMA, not the product or uArch. Which is still an issue with Zen 2. Only better managed.
- shituonui 5y agoThey made a tradeoff of having higher and less uniform memory access. This was not a failure. It was a decision that paid off.
- hajile 5y agoThere might be an I/O die. I'd go so far as to say it could even be an I/O die with a bunch more cache too.