> ... is there something else going on in this case? There is: the term comes from general CPU design terminology and is not specific to RISC-V, although Googl

> ... is there something else going on in this case? There is: the term comes from general CPU design terminology and is not specific to RISC-V, although Google does find some RISC-V-specific materials for me given your query[1–3]. Look for micro- and macro-op fusion in Agner Fog’s manuals[4] or Wikichip[5], for example. [1]: https://riscv.org/wp-content/uploads/2016/07/Tue1130celio-fusion-finalV2.pdf https://riscv.org/wp-content/uploads/2016/07/Tue1130celio-fu... [2]: https://reviews.llvm.org/D73643 https://reviews.llvm.org/D73643 [3]: https://erik-engheim.medium.com/the-genius-of-risc-v-microprocessors-b19d735abaa6 https://erik-engheim.medium.com/the-genius-of-risc-v-micropr... [4]: https://www.agner.org/optimize/#manuals https://www.agner.org/optimize/#manuals [5]: https://en.wikichip.org/wiki/macro-operation_fusion https://en.wikichip.org/wiki/macro-operation_fusion