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> Let's look at some examples (7 instructions vs 2 vs 2) Isn't this the classic RISC vs CISC problem? Comparing x86/ARM to RISC-V feels like Apples to Grains
by tomxor 5y ago
> Let's look at some examples (7 instructions vs 2 vs 2)
Isn't this the classic RISC vs CISC problem?
Comparing x86/ARM to RISC-V feels like Apples to Grains of Rice.
If RISC-V was born out of a need for an open source embedded ISA, would the ISA not need to remain very RISC-like to accommodate implementations with fewer available transistors... Or is this an outdated assumption?
- mhh__ 5y agoIt's not exactly RISC VS CISC. Maybe SISC - "Simplified" instruction set computing, perhaps. ARM isn't exactly super complicated in this particular aspect (it is elsewhere), but in this case the designers basically chose to make branches simpler at the expense of code that needs to check overflows (or flags more generally) RISC-V was born partly out of a desire for a teaching ISA, also, so simplicity is a boon in that context too.