Overflow bailout is 1 instruction in RISC-V (same as x86/ARM) if either the addition is unsigned or you know the sign of one of the operands, one of which is us

Overflow bailout is 1 instruction in RISC-V (same as x86/ARM) if either the addition is unsigned or you know the sign of one of the operands, one of which is usually the case. (If neither is the case, it's 3 instructions.) And I believe RISC-V supports 1-lane vectors through its variable-width vector feature, which an implementation could optimize if it wanted to (though I agree with you that RISC-V should just grow a proper add-with-carry instruction).