You ignore compressed instructions on RISC-V which 64-bit ARM does not have. And if you compare 32-bit CPUs then RISC-V has twice as many registers reducing th

You ignore compressed instructions on RISC-V which 64-bit ARM does not have. And if you compare 32-bit CPUs then RISC-V has twice as many registers reducing the number of instructions needed to read and write from memory. RISC-V branching takes less space and so does vector instructions. There are many case like that which adds up end results in RISC-V having the most dense ISA in all studies when using compressed instructions.