Never heard of SuperH. I see it has branch delay slots, which is a seemingly clever but terrible idea. It's one of the reasons RISC-V quickly overtook OpenRISC

Never heard of SuperH. I see it has branch delay slots, which is a seemingly clever but terrible idea. It's one of the reasons RISC-V quickly overtook OpenRISC in popularity I think. Not having anything that stands out is perhaps a good thing. Being "clever" with the ISA tends to bite you when implementing OoO superscalar cores.