3 ms·
Doesn't RISC-V have an add-with-carry instruction as part of the vector extension? I see it listed here: https://github.com/riscv/riscv-v-spec/releases/tag/v1.0
by pcwalton 5y ago
Doesn't RISC-V have an add-with-carry instruction as part of the vector extension? I see it listed here: https://github.com/riscv/riscv-v-spec/releases/tag/v1.0 https://github.com/riscv/riscv-v-spec/releases/tag/v1.0
- monocasa 5y agoAfaict that's only for operations the vector register file. Most of the complaints about the lack of addc/subc are around how they're heavily used in JITs for languages that want to speculatively optimize multi precision arthimetic into the integer register file for their regular integer ops. JavaScript, a lot of Lisps, the MLs all fit into that space.
- pcwalton 5y agoSure, but this email is in the context of GMP, which should be using the vector extension, no?
- monocasa 5y agoI don't think so; most of the users I know of for the integer side of GMP are compilers/runtimes. An apt rdepends on the gmp packages in Ubuntu only shows stuff like ocaml, and I know gcc vendors it. Edit: Another place you see this kind of arthimetic is crypto, but those specific use cases (Diffie Hellman, RSA, a few others) don't tend to be vectorized. You have one op you're trying to work through with large integers, and there's the carry dependency on each partial op. The carry depdent crypto algorithms aren't typically vectorisable.
- pcwalton 5y agoI'm a bit confused. First, JavaScript doesn't use bignum arithmetic much. JS Numbers are doubles. JavaScript JITs do speculatively use integers where possible, but this workload doesn't need add-with-carry, just efficient overflow detection (which is a problem with RISC-V, but not the problem we're discussing here). It could be a problem for Lisp and ML, but these are hardly common languages. And as for crypto, couldn't you use the vector registers to do scalar ops?
- monocasa 5y agoJS numbers speculatively using integers in practice rely on the carry flag for cheap overflow bailout checks. Maybe if the overflow check didn't have the same problem, they'd look at that instead, but I don't see why they should have to switch if it doesn't gain them anything. And there's tons of reasons why using one lane of vector units as scalar ops is an issue. Power, lack of ubiquitous vector units, their pipeline is commonly decoupled from the integer unit making branches goofy, etc.
- pcwalton 5y agoOverflow bailout is 1 instruction in RISC-V (same as x86/ARM) if either the addition is unsigned or you know the sign of one of the operands, one of which is usually the case. (If neither is the case, it's 3 instructions.) And I believe RISC-V supports 1-lane vectors through its variable-width vector feature, which an implementation could optimize if it wanted to (though I agree with you that RISC-V should just grow a proper add-with-carry instruction).