3 ms·
A bit of a computer history question: I have never looked at the ISA of the Alpha (referenced in post), but RISC V has always struck me as being nearly identica
by Teknoman117 5y ago
A bit of a computer history question: I have never looked at the ISA of the Alpha (referenced in post), but RISC V has always struck me as being nearly identical to (early) MIPS, just without the HI and LO registers for multiply results and the addition of variable length instruction support, even if the core ISA doesn't use them.
MIPS didn't have a flag register either and depended on a dedicated zero register and slt instructions (set if less than)
- okl 5y agoI bet this article on RISC-V's genealogy is interesting for you: https://live-risc-v.pantheonsite.io/wp-content/uploads/2016/02/EECS-2016-6.pdf https://live-risc-v.pantheonsite.io/wp-content/uploads/2016/...
- cpeterso 5y agoAndrew Waterman's thesis ("Design of the RISC-V Instruction Set Architecture") has a very approachable comparison of RISC-V to MIPS, SPARC, Alpha, ARMv7, ARMv8, OpenRISC, and x86: https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-1.pdf https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-...
- dfox 5y agoThe no flags at all part is clearly inspired by Alpha including the rationale of flags being detrimental to OoO implementation. MIPS is classical RISC design that was not designed to be OoO-friendly at all and is simply designed for ease of straightforward pipelined implementation. The reason why it does not have flags probably simply comes down to the observation that you don't need flags for C.
- deleted 5y ago[deleted]
- userbinator 5y agoYes, that's exactly my thought every time it comes out; RISC-V is likely to displace MIPS everywhere performance doesn't matter, but it'll have a hard time competing with ARM or x86 on that.