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Few years ago, I designed my own ISA. In that time I investigated design decisions in lots of ISAs and compared them. There was nothing in the RISC-V instructio
by okl 5y ago
Few years ago, I designed my own ISA. In that time I investigated design decisions in lots of ISAs and compared them. There was nothing in the RISC-V instruction set that stood out to me, like for example, the SuperH instruction set, which is remarkably well designed.
Edit: Don't get me wrong, I don't think RISC-V is "garbage" or anything like that. I just think it could have been better. But of course, most of an architecture's value comes from its ecosystem and the time spent optimizing and tailoring everything...
- AlotOfReading 5y agoMy memories of SuperH are a bit different. Yeah, it's cleaner than ARM, but the delay slots, hardware division, and the tiny register file among others made life unnecessarily difficult. A lot of those design decisions didn't hold up well over time.
- okl 5y agoInteresting! From which perspective? Implementing the ISA, compiler or applications? Did you write machine language or compiled?
- AlotOfReading 5y agoMainly system level and higher, but a bit of all three, I suppose. I was helping reverse engineer a customized SH chip and ended up implementing a small VM and optimized system libraries/utilities afterwards. Most of the time was spent in assembly, with some machine code and C on either side.
- okl 5y agoThanks for your insight.
- mlyle 5y agoIt's not really too unusual of a vantage point. SH was clean in some ways, but delay slots are annoying for anything that speculatively executes (which sets a bit of a performance ceiling without a lot of complexity), and more registers are generally better.
- audunw 5y agoNever heard of SuperH. I see it has branch delay slots, which is a seemingly clever but terrible idea. It's one of the reasons RISC-V quickly overtook OpenRISC in popularity I think. Not having anything that stands out is perhaps a good thing. Being "clever" with the ISA tends to bite you when implementing OoO superscalar cores.
- nocat 5y agoWhat are the particularly good design features of SuperH? (As compared to, say, MIPS?) What sticks in my mind from my limited exposure to SuperH is that there's no load immediate instruction, so you have to do a PC-relative load instead. It was clearly optimized for compiled rather than handwritten code!
- okl 5y ago> What sticks in my mind from my limited exposure to SuperH is that there's no load immediate instruction, so you have to do a PC-relative load instead. SuperH has a mov #imm, Rx that can take an 8-bit #imm. But you're right, literal pools were used just like on ARM. Things I liked about SuperH: 16 bit fixed-width insn format (except for some SH2A and DSP ops), T flag for bit manipulation ops, GBR to enable scaled loads with offset, xtrct instruction, single-cycle division insns (div0, div1), MAC insns. In terms of code density SH was quite effective, see here http://web.eece.maine.edu/~vweaver/papers/iccd09/iccd09_density.pdf http://web.eece.maine.edu/~vweaver/papers/iccd09/iccd09_dens... or here http://www.deater.net/weave/vmwprod/asm/ll/ll.html http://www.deater.net/weave/vmwprod/asm/ll/ll.html