It's best to think of RISCV not as a single ISA (= instruction set architecture), but a parametric ISA. The extensions are parameters. RISCV offers lots of of

It's best to think of RISCV not as a single ISA (= instruction set architecture), but a parametric ISA. The extensions are parameters. RISCV offers lots of official extensions to choose from, such as M, A, F, D, P, V, .... In addition you have the 32 vs 64 bit data width parameter. Any specific ISA will have to instantiate those parameters, like e.g. so: RISCV32MFP or RISCV64MAF. Any implementation of e.g. RISCV64MAF will have to implement in silicon exactly those assembly command (and supporting features) that the M, A and F extension demand, with 64 bit register width. Like in OO-programming the class constructors take arguments that parameterise the created object. ------ Regarding an implementation, given that RISCV is an ISA, not an ISA implementation, you need to provide a functional model. The official standard is [1] but it's a bit behind the ratified extensions. For example [2] defines the (ISA-visible) registers, while [3] gives you the instruction decoding and execution clause for the most base instruction set. [4] describes part of one of the available address translation modes (for the 32 bit variant of the ISA). Note: in modern processors page-table walks are hardware accelerated, so OS and processor need to use the same format here, which is why this is part of the ISA. [1] https://github.com/riscv/sail-riscv/tree/master/model https://github.com/riscv/sail-riscv/tree/master/model [2] https://github.com/riscv/sail-riscv/blob/master/model/riscv_regs.sail https://github.com/riscv/sail-riscv/blob/master/model/riscv_... [3] https://github.com/riscv/sail-riscv/blob/master/model/riscv_insts_base.sail https://github.com/riscv/sail-riscv/blob/master/model/riscv_... [4] https://github.com/riscv/sail-riscv/blob/master/model/riscv_vmem_sv32.sail https://github.com/riscv/sail-riscv/blob/master/model/riscv_...