5 ms·

I'd love to hear what people have to say about the vector instructions. I've always found that SIMD on x86was quite clunky and I heard risc-v vectors are very d

• sanxiyn 5y ago
  Yes it is. On x86, SSE is 128-bit and AVX is 256-bit and AVX-512 is 512-bit. RISC-V V extension handles all vector lengths uniformly: vector add is the same instruction no matter vector length.
  • petermcneeley 5y ago
    What about a vector of 1 element
    • brucehoult 5y ago
      Yes, no problem. Machines with any size vector registers handle code specifying vector length of 1 (or 0!) no problem. If you really want to make a machine with vector registers that hold only one element then that will work too, except for a handful of instructions that simply don't make sense in that case (unless you use the LMUL feature): vector permute register, slide up, slide down. CPUs intended to run standard operating systems with shrink-wrapped software are constrained in the RVA22 profile to provide vector registers of at least 128 bits and no more than 65536 bits. But if you're doing some custom embedded custom CPU then you can make the vector registers the same size as the integer registers (32 or 64 bits). Note that if you do that, you can still usefully do vector operations on chars and shorts, and you can also set LMUL=8 to give you effectively four vector registers of 256 or 512 bits each (which might or migth not be processed serially).
• d_tr 5y ago
  The extension is agnostic with respect to the actual width of the chip's registers, and you also won't have to separately account for the "last iteration" where you have not enough elements to fill a register, or at least it will be more convenient. It also has strided load and store as well as scatter and gather. This is all I remember, there is probably more.
• _chris_ 5y ago
  Very different. RISC-V's vectors (RVV) are "variable length", so the programmer can request a length and the machine tells you what it can give you. Different machine versions can change the underlying vector size and the code Will Just Work. This is different from "fixed-width SIMD" which has a hard-coded vector length. To make things more challenging for the programmer/compiler, I believe most x86 SIMD versions also don't provide a "mask" register, so you're stuck with using all vector elements (AVX512 added masks). Each has its advantages and disadvantages (esp. on the design complexity vs programmer/compiler interface complexity). RVV also provides a mechanism to reconfigure the register file, ganging logical registers together to get longer effective vector lengths.
  • volta83 5y ago
    Can you change the "shape of the vectors? e.g. 1x16 vs 4x4 to support vectors and matrices?
    • crest 5y ago
      You have widening operations e.g. 16x16->32 bit multiplications and can reduce number of available registers to get longer vectors, but among the really interesting ones are fault only first load and masked instructions that enable the vector unit to work on things like null terminated strings. The specification includes vectorized strlen/strcmp/strcpy/strncpy implementations as examples. Most existing (packed) SIMD instruction sets aren't useful for these common functions.
      • jcranmer 5y ago
        Given the number of implementations of str* routines in https://github.com/bminor/glibc/tree/master/sysdeps/x86_64/multiarch https://github.com/bminor/glibc/tree/master/sysdeps/x86_64/m..., maybe you might want to revisit your last statement. PCMP/MOVMSK work well enough for finding the trailing NUL.
        • crest 5y ago