I have no idea for Riscv specifically, but x86/amd64 have a lot of optional instructions (I'm mostly aware of vector stuff like SSE, AVX but I'm sure there are

I have no idea for Riscv specifically, but x86/amd64 have a lot of optional instructions (I'm mostly aware of vector stuff like SSE, AVX but I'm sure there are other stuff). On the programming side, you can detect at runtime feature support and use specific code path accordingly, or decide at compile time that you require a specific CPU feature and then your binary will just not work on CPUs without the feature.