4 ms·

I wonder how an M1 Max assembly version would fare.

• faeyanpiraat 5y ago
  Before running the code, make sure your CPU does support AVX2. Most 64-bit Intel and AMD CPUs should. ARM CPUs, like those found in newer Apple computers, Smartphones or Raspberry Pis, won't support AVX2.
  • comonoid 5y ago
    ARM CPUs have NEON. I cannot say if NEON has all equivalent commands, however, the threadstarter is talking about complete rewrite, not just running it as is.
    • innocenat 5y ago
      NEON only has 128bit register. AVX has 256 bit register.
      • comonoid 5y ago
        Yep, it will most likely require to reorganize the program, but by itself it doesn't necessary mean that the result will be slower.
  • Tepix 5y ago
    That sentence seems silly. ARM assembly and x86-64 assembly are two different beasts. Running the x86-64 code using Rosetta 2 emulation seems counter-intuitive as well if you want to get the fastest possible result on that machine.
• Croftengea 5y ago
  ARM64 SIMD instructions perform in the same ballpark, see this: https://news.ycombinator.com/item?id=25408853 https://news.ycombinator.com/item?id=25408853
• SekstiNi 5y ago
  The Firestorm cores are capable of issuing two 128bit stores per cycle [1], giving a bandwidth of 102.4 GBps. This matches the experiments by Andrei with mixed reads/writes [2], and I have personally verified that it is attainable for pure write workloads to L1 as well as L2. This does not mean 102.4 GBps is achievable on a single core, but if L2 bandwidth is the limiting factor it very well could be. [1] https://dougallj.github.io/applecpu/firestorm.html https://dougallj.github.io/applecpu/firestorm.html [2] https://www.anandtech.com/show/17024/apple-m1-max-performance-review/2 https://www.anandtech.com/show/17024/apple-m1-max-performanc...