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The fact that CPUs internally have microcode doesn't mean there's a different RISC CPU lurking underneath that you could just take the lid off of. In particular
by Sesse__ 5y ago
The fact that CPUs internally have microcode doesn't mean there's a different RISC CPU lurking underneath that you could just take the lid off of. In particular, the instruction decoder, which is what you're proposing to change, is not implemented in microcode; that would just be way too slow.
An x86 CPU is made for executing x86 instructions.
- LargoLasskhyfv 5y agoThat would depend on how and what you can feed it? Say if you'd got a backend for something like LLVM, which emits the µOps directly, thereby circumventing the instruction decoder, if technically/architecturally possible at all. Instead of going through the instruction decoder.