> DRAM architecture fu is just as important, IMHO Well, I happen to know about that stuff out of interest, but I wouldn't claim it's very useful knowledge for

> DRAM architecture fu is just as important, IMHO Well, I happen to know about that stuff out of interest, but I wouldn't claim it's very useful knowledge for a programmer. The top-level cache (L2 or L3) communicates in big chunks with the DRAM controller so that you are insulated from the details of modern DRAMs like double pumping, burst mode, page sizing, channels, banks, etc.