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Reading the article, it seems the TM only work within a single core for now, not across cores. "IBM only implemented transactional memory within the confines o
by ww520 15y ago
Reading the article, it seems the TM only work within a single core for now, not across cores.
"IBM only implemented transactional memory within the confines of a single chip using a tagging scheme on the chip's level-two cache memory."
- rbanffy 15y agoI saw 18 cores and 16 L2 caches. Either two cores have no L2 or the L2 banks are somehow shared. From the article it's not clear if two cores can access a single L2 cache concurrently. My interpretation is that the transactional memory works for all cores in the chip.