This is an amazing project considering the scope of work required on both sides of the aisle -- HW and SW. I find choice of RISC-V pretty interesting for this

This is an amazing project considering the scope of work required on both sides of the aisle -- HW and SW. I find choice of RISC-V pretty interesting for this use case as it's a fixed-size ISA and there is a significant amount of of auxiliary data usually passed from drivers to HW in typical GPU settings, even for GPGPU scenarios alone. If you look at one of their papers, it shows how they pass extra texture parameters via CSRs. I think this might come to be bottleneck and limiting factor in the design for future expansions. I am currently doing a similar work (>10x smaller in comparison) on a more limited feature set, so I am really curious how it'll turn out to be.