3 ms·
So does the CPU raise a hardware interrupt when it detects conflicts in the transactional memory? Are there new instructions (or flags) for preparing a L1/L2 c
by ww520 15y ago
So does the CPU raise a hardware interrupt when it detects conflicts in the transactional memory? Are there new instructions (or flags) for preparing a L1/L2 cache as TM?
The interrupt can be mapped to an exception to be raised in a language. Clojure and others can integrate with it easily.
Having TM in a single CPU is a good step in the right direction. The holy grail would be having TM with multiple CPU.
- deleted 15y ago[deleted]
- rbanffy 15y ago> The holy grail would be having TM with multiple CPU. Well... This chip has 18 cores.
- ww520 15y agoReading the article, it seems the TM only work within a single core for now, not across cores. "IBM only implemented transactional memory within the confines of a single chip using a tagging scheme on the chip's level-two cache memory."
- rbanffy 15y agoI saw 18 cores and 16 L2 caches. Either two cores have no L2 or the L2 banks are somehow shared. From the article it's not clear if two cores can access a single L2 cache concurrently. My interpretation is that the transactional memory works for all cores in the chip.