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IBM plants transactional memory in CPU

36 points by yurisagalov 15y ago

51Cards 15y ago
If I may wander off topic for a sec on the specifics of this particular article, I have to say that I really love IBM. Often when they hit the tech news for something it's not just an upgrade or an iteration, but frequently it has them attempting to find the next paradigm shift in core computing. Entirely new CPU architectures, inventing or applying never before used technologies, etc. This is innovation and I really take my hat off to them for the amount of effort they put into pure computing research and prototyping. Edit, yes I do also realize that in the specifics of this article Sun was first to implement this.
ww520 15y ago
So does the CPU raise a hardware interrupt when it detects conflicts in the transactional memory? Are there new instructions (or flags) for preparing a L1/L2 cache as TM? The interrupt can be mapped to an exception to be raised in a language. Clojure and others can integrate with it easily. Having TM in a single CPU is a good step in the right direction. The holy grail would be having TM with multiple CPU.
- deleted 15y ago
  [deleted]
- rbanffy 15y ago
  > The holy grail would be having TM with multiple CPU. Well... This chip has 18 cores.
  - ww520 15y ago
    Reading the article, it seems the TM only work within a single core for now, not across cores. "IBM only implemented transactional memory within the confines of a single chip using a tagging scheme on the chip's level-two cache memory."
    - rbanffy 15y ago
      I saw 18 cores and 16 L2 caches. Either two cores have no L2 or the L2 banks are somehow shared. From the article it's not clear if two cores can access a single L2 cache concurrently. My interpretation is that the transactional memory works for all cores in the chip.
rbanffy 15y ago
And this is one of the reasons why Wintel depresses me so much - I wouldn't have much use for the 18 cores, but I would love to have (and there is good reason to assume it would be an improvement) transactional memory. Yet, nobody will have it in mainstream (read cheap) computers before Microsoft decides to support it and that won't come before Windows 9 or 10, 8 years from now.
- gaius 15y ago
  There's STM right now in GHC.
  - rbanffy 15y ago
    Several languages simulate it (I used it with Clojure), but I don't see significant parts of Windows being written in Haskel anytime soon. I'll dig up the link of a study on TM with a Linux kernel as soon as I can and paste it here. It was very interesting.

36 points by yurisagalov 15y ago

If I may wander off topic for a sec on the specifics of this particular article, I have to say that I really love IBM. Often when they hit the tech news for something it's not just an upgrade or an iteration, but frequently it has them attempting to find the next paradigm shift in core computing. Entirely new CPU architectures, inventing or applying never before used technologies, etc. This is innovation and I really take my hat off to them for the amount of effort they put into pure computing research and prototyping. Edit, yes I do also realize that in the specifics of this article Sun was first to implement this.

ww520 15y ago

So does the CPU raise a hardware interrupt when it detects conflicts in the transactional memory? Are there new instructions (or flags) for preparing a L1/L2 cache as TM? The interrupt can be mapped to an exception to be raised in a language. Clojure and others can integrate with it easily. Having TM in a single CPU is a good step in the right direction. The holy grail would be having TM with multiple CPU.

deleted 15y ago
[deleted]
rbanffy 15y ago
> The holy grail would be having TM with multiple CPU. Well... This chip has 18 cores.
- ww520 15y ago
  Reading the article, it seems the TM only work within a single core for now, not across cores. "IBM only implemented transactional memory within the confines of a single chip using a tagging scheme on the chip's level-two cache memory."
  - rbanffy 15y ago
    I saw 18 cores and 16 L2 caches. Either two cores have no L2 or the L2 banks are somehow shared. From the article it's not clear if two cores can access a single L2 cache concurrently. My interpretation is that the transactional memory works for all cores in the chip.

rbanffy 15y ago

And this is one of the reasons why Wintel depresses me so much - I wouldn't have much use for the 18 cores, but I would love to have (and there is good reason to assume it would be an improvement) transactional memory. Yet, nobody will have it in mainstream (read cheap) computers before Microsoft decides to support it and that won't come before Windows 9 or 10, 8 years from now.

gaius 15y ago
There's STM right now in GHC.
- rbanffy 15y ago
  Several languages simulate it (I used it with Clojure), but I don't see significant parts of Windows being written in Haskel anytime soon. I'll dig up the link of a study on TM with a Linux kernel as soon as I can and paste it here. It was very interesting.