6 ms·

What programmers need to know about hardware prefetching?

49 points by tech_junkie 15y ago

rcfox 15y ago
Is this different from caches? If so, the advice also applies to properly using the cache. I've read that cache misses are the biggest source of slow-downs on modern processors. (Sorry, no citation)
- deleted 15y ago
  [deleted]
- tech_junkie 15y ago
  This is related to caches as the author is talked about hardware prefetching from memory to caches, i.e., is the act of fetching in to the cache the data that will be needed in the near future. This reduces cache misses.
zwieback 15y ago
Nice introduction to data prefetching. I don't fully agree with this statement, though: Second, programmers have very little control over instruction placement in memory. Depending on your platform and type of application you may have full control over instruction placement and it might be extremely important to know how to sequence instructions to get maximum performance.
- keeperofdakeys 15y ago
  Assuming he is talking about languages like C, and you don't use inline assembly, I don't see how you can have any control. For anything complex, your compiler will probably do a much better job then you in creating fast assembly.In the case you can do better, you would just inline the code, so you only have control over that small part.
  - deleted 15y ago
    [deleted]
  - zwieback 15y ago
    I was talking about assembly. In DSP applications it's common to worry about the precise sequence of assembly instructions. Compilers are very, very good in general but for new and exotic architectures it's not uncommon to have inner loops in hand-coded assembly. The examples in the article were in a HLL but the site is about chips, the next article about mixing HDLs and HLLs so I thought it was fair pointing out that there's something at the lower levels.
- Hoff 15y ago
  It's certainly possible to have that control via assembler, where folks are programming in that. So strictly speaking, yes, your "may" can be true. For C or another language, here's some related reading on that topic, and where you can get into deep trouble with this: http://www.hpl.hp.com/personal/Hans_Boehm/misc_slides/pldi05_threads.pdf http://www.hpl.hp.com/personal/Hans_Boehm/misc_slides/pldi05... http://www.hpl.hp.com/personal/Hans_Boehm/misc_slides/reordering.pdf http://www.hpl.hp.com/personal/Hans_Boehm/misc_slides/reorde... http://www.hpl.hp.com/techreports/2005/HPL-2005-217R1.pdf http://www.hpl.hp.com/techreports/2005/HPL-2005-217R1.pdf http://www.hpl.hp.com/techreports/2004/HPL-2004-209.pdf http://www.hpl.hp.com/techreports/2004/HPL-2004-209.pdf
squeed 15y ago
The article really only touches on the absolute basics. It would have left me hurting for more specifics. However, I've read Ulrich Drepper's epic paper on modern memory architectures. (http://lwn.net/Articles/259710/ http://lwn.net/Articles/259710/) You should do yourself a favor and read it.
- ChuckMcM 15y ago
  +10, best article on memory ever. If a similar treatment showed up on branch prediction we would have an excellent pair.

49 points by tech_junkie 15y ago

rcfox 15y ago

Is this different from caches? If so, the advice also applies to properly using the cache. I've read that cache misses are the biggest source of slow-downs on modern processors. (Sorry, no citation)

deleted 15y ago
[deleted]
tech_junkie 15y ago
This is related to caches as the author is talked about hardware prefetching from memory to caches, i.e., is the act of fetching in to the cache the data that will be needed in the near future. This reduces cache misses.

zwieback 15y ago

Nice introduction to data prefetching. I don't fully agree with this statement, though: Second, programmers have very little control over instruction placement in memory. Depending on your platform and type of application you may have full control over instruction placement and it might be extremely important to know how to sequence instructions to get maximum performance.

keeperofdakeys 15y ago
Assuming he is talking about languages like C, and you don't use inline assembly, I don't see how you can have any control. For anything complex, your compiler will probably do a much better job then you in creating fast assembly.In the case you can do better, you would just inline the code, so you only have control over that small part.
- deleted 15y ago
  [deleted]
- zwieback 15y ago
  I was talking about assembly. In DSP applications it's common to worry about the precise sequence of assembly instructions. Compilers are very, very good in general but for new and exotic architectures it's not uncommon to have inner loops in hand-coded assembly. The examples in the article were in a HLL but the site is about chips, the next article about mixing HDLs and HLLs so I thought it was fair pointing out that there's something at the lower levels.
Hoff 15y ago
It's certainly possible to have that control via assembler, where folks are programming in that. So strictly speaking, yes, your "may" can be true. For C or another language, here's some related reading on that topic, and where you can get into deep trouble with this: http://www.hpl.hp.com/personal/Hans_Boehm/misc_slides/pldi05_threads.pdf http://www.hpl.hp.com/personal/Hans_Boehm/misc_slides/pldi05... http://www.hpl.hp.com/personal/Hans_Boehm/misc_slides/reordering.pdf http://www.hpl.hp.com/personal/Hans_Boehm/misc_slides/reorde... http://www.hpl.hp.com/techreports/2005/HPL-2005-217R1.pdf http://www.hpl.hp.com/techreports/2005/HPL-2005-217R1.pdf http://www.hpl.hp.com/techreports/2004/HPL-2004-209.pdf http://www.hpl.hp.com/techreports/2004/HPL-2004-209.pdf

squeed 15y ago

The article really only touches on the absolute basics. It would have left me hurting for more specifics. However, I've read Ulrich Drepper's epic paper on modern memory architectures. (http://lwn.net/Articles/259710/ http://lwn.net/Articles/259710/) You should do yourself a favor and read it.

ChuckMcM 15y ago
+10, best article on memory ever. If a similar treatment showed up on branch prediction we would have an excellent pair.