They call them segmentation registers in the source, but it's really paging hardware in the modern parlance. The estabur function in your citation can be seen

They call them segmentation registers in the source, but it's really paging hardware in the modern parlance. The estabur function in your citation can be seen iterating over the whole virtual address spaces (one each for I and D), and setting the permissions for each 8KB page. It's not super clearly written code, but those ap and dp variables are pointers to PTEs. The hardware they're programming against is a KT-11D (compatible) MMU. Here's it's user guide: http://www.bitsavers.org/pdf/dec/pdp11/1140/KT11D_UsersMan.pdf http://www.bitsavers.org/pdf/dec/pdp11/1140/KT11D_UsersMan.p...