This was true of pretty much every CPU generation before the P4. Deeper pipelines result in lower FO4 (and thus higher attainable clock frequency), but a highe

This was true of pretty much every CPU generation before the P4. Deeper pipelines result in lower FO4 (and thus higher attainable clock frequency), but a higher penalty for branch misprediction, among other things. Historically (pre-P4) this was a great tradeoff. The Alpha 21064 was a barn-stormer; it ran at nearly twice the Mhz of its brainiac competitors at the time. This more than made up for a deeper pipeline and simpler execution units. What killed the P4 was that they hit the power wall. Moore's law scaling of gate size no longer resulted in a corresponding scaling of power usage. It is hard to blame the P4 designers too much for this, since people have been prophesying the end of Moore's law since the mid-80s at least. They happened to be designing when it actually happened on power. Current designers should look to that lesson when relying on increasing density... Of course, these lessons are pretty useless, because much like a stock market bubble, Moore's law continues on a given metric until it doesn't. And it is always obvious in retrospect.