The P-III has 8 general purpose registers, just like all pre-64bit x86 CPUs, all the way back to the 8086. x86-64 (aka amd64) CPUs have 16. But it gets a bit

The P-III has 8 general purpose registers, just like all pre-64bit x86 CPUs, all the way back to the 8086. x86-64 (aka amd64) CPUs have 16. But it gets a bit more complicated. I'm talking about (and your references to compilers suggests that you are as well) architectural registers; the things assembly programmers and compiler writers see. The actual register file in the CPU has many more registers on out-of-order CPUs like the Pentium Pro and later; these are physical registers, and are mapped to the architectural registers dynamically by the register renamer. This is done to prevent false dependencies from preventing parallel execution of instructions in the same instruction stream. The work done by the compiler to map live variables into architectural registers is mostly orthogonal to the work the CPU's instruction scheduler does to map architectural registers to physical ones. In some sense, more architectural registers are better, but there are diminishing returns, and eventually other considerations make more worse. x86-64's 16 architectural registers is a pretty good compromise for current generation CPUs. Your comparison between ARM CPUs and x86 is somewhat spurious, since the instruction set defines the architectural registers: 16 for x86-64, 32 for ARM. A given out-of-order implementation can choose whatever number of physical registers gives optimal performance, and given the stakes and available engineering resources, both ARM and Intel/AMD will choose optimal (or exceptionally close to optimal) numbers for this. Long story short, the number of architectural registers is an extremely small part of why ARM is or isn't "pWning" Intel on low power platforms.