There are enormous benefits for any architecture that puts the memory adjacent to the processing units on the same chip. You eliminate the latency of registers

There are enormous benefits for any architecture that puts the memory adjacent to the processing units on the same chip. You eliminate the latency of registers to L1 memory to L2 memory to main memory giving enormous speed improvements. For example, consider a simulation where many cells are hidden from a point of view (graphics) or are slowly changing. An on chip network of simple processors and memory could quickly identify the cells that were probably going to change in this iteration. An attached array of more powerful processors could do the heavy duty processing but using fewer of them. Some people I know got a 100x improvement in image processing by using a chip with a network of simple 18bit floating point processors to eliminate hidden elements in an image. The reduced set of cells could be processed in real time. There is room for lots of interesting products on a budget smaller IBM's, although it is hard to do hardware with the budget of a YC startup.