3 ms·

The same could be said about ASM. You can complete any project with it, the tooling is very good. It will just take much longer and you will have to debug more.

The same could be said about ASM. You can complete any project with it, the tooling is very good. It will just take much longer and you will have to debug more. In that sense no language ever is important. The point of a language is to allow the developer to write code faster and in a more secure manner. In both of these clash is vastly superior to vhdl or verilog. Imagine a world were we would still be stuck with C because people don't understand the point of improving on it. I think this would have had societal level consequences with what we would have been able to do with computers.

laydn 5y ago
But, HOW do you debug Clash? For example, what is the design and debug flow of using Clash to target a Xilinx FPGA? My guess is that you're going to tell me I will have to debug the generated Verilog code?
- rowanG077 5y ago
  I've been using Clash for about 2 years now. I just debug the clash code. As in just use the normal Haskell test tooling. The only reason I ever read the generated HDL is when I make sure I have integrated another IP correctly.
  - tubby12345 5y ago
    qq: i know that for HLS sometimes (most?) the generated HDL is 10x the number of resources (flip-flops?) compared to hand-written HDL. how bad is clash in this respect?
    - rowanG077 5y ago
      Clash is not HLS. You have full control of register placement and pipelining just like VHDL and Verilog. Clash in that sense is not "higher level" then VHDL or Verilog. In some respects you could even say that Clash is "lower level" because you don't write things just right to be inferred correctly. You actually specify what hardware you want. E.g. you write I want a blockram with this size here, and not if I write this specific Verilog the tools will infer a blockram. What Clash gives you is the power and tooling of Haskell.
      - tubby12345 5y ago
        >Clash is not HLS i don't understand - how do you generate the bitstream if you're not generating verilog or vhdl first?
        rowanG077 5y ago
        Clash does generate Verilog or VHDL but the only reason it does this is to interface with vendor tooling. HLS generally means you compile a very high level description of computation to VHDL/Verilog. This high level description doesn't contain hardware details like registers, ram usages, pipelining etc. During the process of HLS the synthesis tool will try to translate this description to a digital circuit. It will itself place registers, rams pipeline as necessary. That is the reason HLS doesn't reach the performance of VHDL/Verilog, these HLS tools just aren't as good as a human making the digital circuit. Clash is not itself coming up with a digital circuit like HLS is doing. The developer is specifying the digital circuit. Just like with VHDL or Verilog. It's just an alternative way of writing it.
        tubby12345 5y ago
        got it - it's like chisel. thanks
        rowanG077 5y ago
        Not exactly. Chisel is a DSL while clash is not. But it's at the same level of circuit design abstraction.
        rowanG077 5y ago
        Looking at your posting history I can be a little more concrete: Chisel is essentially a metaprogramming framework for VHDL/Verilog. Clash is a compiler closely based on GHC that compiles Haskell code, not a DSL defined within Haskell, to VHDL/Verilog.
        tubby12345 5y ago
- gergoerdi 5y ago
  Debugging via high-level simulation is something my book spends a lot of time on. If you look at the sample chapters, you can see that the same Clash code can also be compiled into software Haskell, which you can then interface with non-synthesizable test benches, such as an interactive SDL frontend. So you can take your HDL logic and run it directly, interactively in real time. You can play Pong by compiling the code as software. One level lower, you can use Clash's signal-level simulator. Basically it gives you a synchronous stream of signal values, either as a lazy list (for "offline" simulation), or as an automaton that you can turn the crank on by feeding it the next clock cycle's inputs (for "online" simulation, i.e. where you want to do IO to compute the next input from the previous outputs). So at this level, you'd take your Pong circuit and use the automaton interface of the simulator to feed the virtual "pushbutton" states computed from e.g. keypresses, and then consume the output to do the rendering. Or simulate the whole circuit end-to-end and feed its output into a VGA interpreter, which you also get to write in Haskell. If you need to debug at the Verilog level, you can use Clashilator (https://github.com/gergoerdi/clashilator https://github.com/gergoerdi/clashilator) to automate FFI-ing into a Verilator-generated simulation.

laydn 5y ago

But, HOW do you debug Clash? For example, what is the design and debug flow of using Clash to target a Xilinx FPGA? My guess is that you're going to tell me I will have to debug the generated Verilog code?

rowanG077 5y ago
I've been using Clash for about 2 years now. I just debug the clash code. As in just use the normal Haskell test tooling. The only reason I ever read the generated HDL is when I make sure I have integrated another IP correctly.
- tubby12345 5y ago
  qq: i know that for HLS sometimes (most?) the generated HDL is 10x the number of resources (flip-flops?) compared to hand-written HDL. how bad is clash in this respect?
  - rowanG077 5y ago
    Clash is not HLS. You have full control of register placement and pipelining just like VHDL and Verilog. Clash in that sense is not "higher level" then VHDL or Verilog. In some respects you could even say that Clash is "lower level" because you don't write things just right to be inferred correctly. You actually specify what hardware you want. E.g. you write I want a blockram with this size here, and not if I write this specific Verilog the tools will infer a blockram. What Clash gives you is the power and tooling of Haskell.
    - tubby12345 5y ago
      >Clash is not HLS i don't understand - how do you generate the bitstream if you're not generating verilog or vhdl first?
      - rowanG077 5y ago
        Clash does generate Verilog or VHDL but the only reason it does this is to interface with vendor tooling. HLS generally means you compile a very high level description of computation to VHDL/Verilog. This high level description doesn't contain hardware details like registers, ram usages, pipelining etc. During the process of HLS the synthesis tool will try to translate this description to a digital circuit. It will itself place registers, rams pipeline as necessary. That is the reason HLS doesn't reach the performance of VHDL/Verilog, these HLS tools just aren't as good as a human making the digital circuit. Clash is not itself coming up with a digital circuit like HLS is doing. The developer is specifying the digital circuit. Just like with VHDL or Verilog. It's just an alternative way of writing it.
        tubby12345 5y ago
        got it - it's like chisel. thanks
        rowanG077 5y ago
        Not exactly. Chisel is a DSL while clash is not. But it's at the same level of circuit design abstraction.
        rowanG077 5y ago
        Looking at your posting history I can be a little more concrete: Chisel is essentially a metaprogramming framework for VHDL/Verilog. Clash is a compiler closely based on GHC that compiles Haskell code, not a DSL defined within Haskell, to VHDL/Verilog.
        tubby12345 5y ago
gergoerdi 5y ago
Debugging via high-level simulation is something my book spends a lot of time on. If you look at the sample chapters, you can see that the same Clash code can also be compiled into software Haskell, which you can then interface with non-synthesizable test benches, such as an interactive SDL frontend. So you can take your HDL logic and run it directly, interactively in real time. You can play Pong by compiling the code as software. One level lower, you can use Clash's signal-level simulator. Basically it gives you a synchronous stream of signal values, either as a lazy list (for "offline" simulation), or as an automaton that you can turn the crank on by feeding it the next clock cycle's inputs (for "online" simulation, i.e. where you want to do IO to compute the next input from the previous outputs). So at this level, you'd take your Pong circuit and use the automaton interface of the simulator to feed the virtual "pushbutton" states computed from e.g. keypresses, and then consume the output to do the rendering. Or simulate the whole circuit end-to-end and feed its output into a VGA interpreter, which you also get to write in Haskell. If you need to debug at the Verilog level, you can use Clashilator (https://github.com/gergoerdi/clashilator https://github.com/gergoerdi/clashilator) to automate FFI-ing into a Verilator-generated simulation.