13 ms·

I am having trouble understanding the usefulness of all these new pseudo-HDL languages. In all the projects that I've worked on, the choice of HDL (which was 9

by laydn 5y ago

I am having trouble understanding the usefulness of all these new pseudo-HDL languages. In all the projects that I've worked on, the choice of HDL (which was 95% of the time, Verilog, for the rest, VHDL), was never actually 'important'; the language features were never critical to the completion of the project. Verilog is fully adequate for any kind of serious HDL development. What mattered were, the tooling, IDEs, debuggers, timing analysis tools, verification infrastructure, the IP ecosystem, etc. Perhaps I am getting old but I just can not see how these new languages can be a serious alternative to Verilog/VHDL.

rowanG077 5y ago
The same could be said about ASM. You can complete any project with it, the tooling is very good. It will just take much longer and you will have to debug more. In that sense no language ever is important. The point of a language is to allow the developer to write code faster and in a more secure manner. In both of these clash is vastly superior to vhdl or verilog. Imagine a world were we would still be stuck with C because people don't understand the point of improving on it. I think this would have had societal level consequences with what we would have been able to do with computers.
- laydn 5y ago
  But, HOW do you debug Clash? For example, what is the design and debug flow of using Clash to target a Xilinx FPGA? My guess is that you're going to tell me I will have to debug the generated Verilog code?
  - rowanG077 5y ago
    I've been using Clash for about 2 years now. I just debug the clash code. As in just use the normal Haskell test tooling. The only reason I ever read the generated HDL is when I make sure I have integrated another IP correctly.
    - tubby12345 5y ago
      qq: i know that for HLS sometimes (most?) the generated HDL is 10x the number of resources (flip-flops?) compared to hand-written HDL. how bad is clash in this respect?
      - rowanG077 5y ago
        Clash is not HLS. You have full control of register placement and pipelining just like VHDL and Verilog. Clash in that sense is not "higher level" then VHDL or Verilog. In some respects you could even say that Clash is "lower level" because you don't write things just right to be inferred correctly. You actually specify what hardware you want. E.g. you write I want a blockram with this size here, and not if I write this specific Verilog the tools will infer a blockram. What Clash gives you is the power and tooling of Haskell.
        tubby12345 5y ago
        >Clash is not HLS i don't understand - how do you generate the bitstream if you're not generating verilog or vhdl first?
        rowanG077 5y ago
        Clash does generate Verilog or VHDL but the only reason it does this is to interface with vendor tooling. HLS generally means you compile a very high level description of computation to VHDL/Verilog. This high level description doesn't contain hardware details like registers, ram usages, pipelining etc. During the process of HLS the synthesis tool will try to translate this description to a digital circuit. It will itself place registers, rams pipeline as necessary. That is the reason HLS doesn't reach the performance of VHDL/Verilog, these HLS tools just aren't as good as a human making the digital circuit. Clash is not itself coming up with a digital circuit like HLS is doing. The developer is specifying the digital circuit. Just like with VHDL or Verilog. It's just an alternative way of writing it.
        5y ago
  - gergoerdi 5y ago
    Debugging via high-level simulation is something my book spends a lot of time on. If you look at the sample chapters, you can see that the same Clash code can also be compiled into software Haskell, which you can then interface with non-synthesizable test benches, such as an interactive SDL frontend. So you can take your HDL logic and run it directly, interactively in real time. You can play Pong by compiling the code as software. One level lower, you can use Clash's signal-level simulator. Basically it gives you a synchronous stream of signal values, either as a lazy list (for "offline" simulation), or as an automaton that you can turn the crank on by feeding it the next clock cycle's inputs (for "online" simulation, i.e. where you want to do IO to compute the next input from the previous outputs). So at this level, you'd take your Pong circuit and use the automaton interface of the simulator to feed the virtual "pushbutton" states computed from e.g. keypresses, and then consume the output to do the rendering. Or simulate the whole circuit end-to-end and feed its output into a VGA interpreter, which you also get to write in Haskell. If you need to debug at the Verilog level, you can use Clashilator (https://github.com/gergoerdi/clashilator https://github.com/gergoerdi/clashilator) to automate FFI-ing into a Verilator-generated simulation.
gnull 5y ago
Clash is not pseudo, it's actual HDL. Right now it compiles to Verilog, yes, but this is minor a technicality. > the choice of HDL (which was 95% of the time, Verilog, for the rest, VHDL), was never actually 'important'; the language features were never critical to the completion of the project Because both are equally bad, and have little meaningful difference in their features. > Verilog is fully adequate for any kind of serious HDL development. This confirms my past experience of interacting with hardware people. They have extremely low standard for their programming languages and tooling in general, and don't like reflecting on these too much. They just suck it up and do the job, no matter what. My Verilog just quietly accepts the code which assigns values to a wire which is declared as input? I guess it's my fault, I will just be more careful in the future not to do that again. My Verilog doesn't allow parametrizing modules with anything other than natural numbers? Well, I'll just duplicate code, that's how we always did it. My Verilog has no types other than "wire" and "array of wires" (and also allows assigning array[2][3] to array[3][2] emitting no warning)? It's fine, I will just try to keep in mind what data I have in which wires and try to make sure I never mix things up. My Verilog uses pseudo-imperative code with "assignments" in it to describe a network of flipflops with combinational logic between them? It's ok, I will just train my brain to convert between the two even though there's no good reason for Verilog to be like that. My Verilog has constructions which are synthesizable only when used in one very specific way, instead of clearly differentiating between synthesizable (actual hardware) and un-synthesizable (imperative testing code)? It's ok, I will just remember the details. My Verilog produces so much noise in the build logs that nobody actually reads it unless something breaks? I guess I just have to be more careful or write more testbenches. > I just can not see how these new languages can be a serious alternative to Verilog/VHDL This is learned helplessness. Clash has better, more natural abstractions for the wires and flipflops. Combinational and sequential logic are clearly separated. It also uses many primitives of Haskell which make your code more compact, easier to read and verify. You can parameterize modules with anything, including other modules, this drastically reduces code duplication and lets you manage the code on a higher level (while still seeing how does it correspond to bits and wires).
- laydn 5y ago
  It's not that we have a low standard, it's that we are bound by the full suite of tools that are provided to us in order to achieve our design objective. When I am close to tapeout and I am moving a single gate across a flip flop in order to extract the final few Mhz out of the design, and my formal equivalence checker only understands Verilog, I will have to use Verilog. I suppose my benchmark in assessing the capabilities of this -or any- language and its ecosystem is the following : Can you use Clash in the design of a reasonably complex chip from scratch (HDL to tapeout)?
exdsq 5y ago
I'm looking at it through another lens - a way to improve my intermediate haskell and learn about HDL. Maybe they're pushing for commercial use but there are alternative reasons to be interested in this too!
qwerty456127 5y ago
The purpose of making anything Haskell-based probably is making it mathematically verifiable. Isn't it?

by laydn 5y ago

rowanG077 5y ago

The same could be said about ASM. You can complete any project with it, the tooling is very good. It will just take much longer and you will have to debug more. In that sense no language ever is important. The point of a language is to allow the developer to write code faster and in a more secure manner. In both of these clash is vastly superior to vhdl or verilog. Imagine a world were we would still be stuck with C because people don't understand the point of improving on it. I think this would have had societal level consequences with what we would have been able to do with computers.

laydn 5y ago
But, HOW do you debug Clash? For example, what is the design and debug flow of using Clash to target a Xilinx FPGA? My guess is that you're going to tell me I will have to debug the generated Verilog code?
- rowanG077 5y ago
  I've been using Clash for about 2 years now. I just debug the clash code. As in just use the normal Haskell test tooling. The only reason I ever read the generated HDL is when I make sure I have integrated another IP correctly.
  - tubby12345 5y ago
    qq: i know that for HLS sometimes (most?) the generated HDL is 10x the number of resources (flip-flops?) compared to hand-written HDL. how bad is clash in this respect?
    - rowanG077 5y ago
      Clash is not HLS. You have full control of register placement and pipelining just like VHDL and Verilog. Clash in that sense is not "higher level" then VHDL or Verilog. In some respects you could even say that Clash is "lower level" because you don't write things just right to be inferred correctly. You actually specify what hardware you want. E.g. you write I want a blockram with this size here, and not if I write this specific Verilog the tools will infer a blockram. What Clash gives you is the power and tooling of Haskell.
      - tubby12345 5y ago
        >Clash is not HLS i don't understand - how do you generate the bitstream if you're not generating verilog or vhdl first?
        rowanG077 5y ago
        Clash does generate Verilog or VHDL but the only reason it does this is to interface with vendor tooling. HLS generally means you compile a very high level description of computation to VHDL/Verilog. This high level description doesn't contain hardware details like registers, ram usages, pipelining etc. During the process of HLS the synthesis tool will try to translate this description to a digital circuit. It will itself place registers, rams pipeline as necessary. That is the reason HLS doesn't reach the performance of VHDL/Verilog, these HLS tools just aren't as good as a human making the digital circuit. Clash is not itself coming up with a digital circuit like HLS is doing. The developer is specifying the digital circuit. Just like with VHDL or Verilog. It's just an alternative way of writing it.
        5y ago
- gergoerdi 5y ago
  Debugging via high-level simulation is something my book spends a lot of time on. If you look at the sample chapters, you can see that the same Clash code can also be compiled into software Haskell, which you can then interface with non-synthesizable test benches, such as an interactive SDL frontend. So you can take your HDL logic and run it directly, interactively in real time. You can play Pong by compiling the code as software. One level lower, you can use Clash's signal-level simulator. Basically it gives you a synchronous stream of signal values, either as a lazy list (for "offline" simulation), or as an automaton that you can turn the crank on by feeding it the next clock cycle's inputs (for "online" simulation, i.e. where you want to do IO to compute the next input from the previous outputs). So at this level, you'd take your Pong circuit and use the automaton interface of the simulator to feed the virtual "pushbutton" states computed from e.g. keypresses, and then consume the output to do the rendering. Or simulate the whole circuit end-to-end and feed its output into a VGA interpreter, which you also get to write in Haskell. If you need to debug at the Verilog level, you can use Clashilator (https://github.com/gergoerdi/clashilator https://github.com/gergoerdi/clashilator) to automate FFI-ing into a Verilator-generated simulation.

gnull 5y ago

Clash is not pseudo, it's actual HDL. Right now it compiles to Verilog, yes, but this is minor a technicality. > the choice of HDL (which was 95% of the time, Verilog, for the rest, VHDL), was never actually 'important'; the language features were never critical to the completion of the project Because both are equally bad, and have little meaningful difference in their features. > Verilog is fully adequate for any kind of serious HDL development. This confirms my past experience of interacting with hardware people. They have extremely low standard for their programming languages and tooling in general, and don't like reflecting on these too much. They just suck it up and do the job, no matter what. My Verilog just quietly accepts the code which assigns values to a wire which is declared as input? I guess it's my fault, I will just be more careful in the future not to do that again. My Verilog doesn't allow parametrizing modules with anything other than natural numbers? Well, I'll just duplicate code, that's how we always did it. My Verilog has no types other than "wire" and "array of wires" (and also allows assigning array[2][3] to array[3][2] emitting no warning)? It's fine, I will just try to keep in mind what data I have in which wires and try to make sure I never mix things up. My Verilog uses pseudo-imperative code with "assignments" in it to describe a network of flipflops with combinational logic between them? It's ok, I will just train my brain to convert between the two even though there's no good reason for Verilog to be like that. My Verilog has constructions which are synthesizable only when used in one very specific way, instead of clearly differentiating between synthesizable (actual hardware) and un-synthesizable (imperative testing code)? It's ok, I will just remember the details. My Verilog produces so much noise in the build logs that nobody actually reads it unless something breaks? I guess I just have to be more careful or write more testbenches. > I just can not see how these new languages can be a serious alternative to Verilog/VHDL This is learned helplessness. Clash has better, more natural abstractions for the wires and flipflops. Combinational and sequential logic are clearly separated. It also uses many primitives of Haskell which make your code more compact, easier to read and verify. You can parameterize modules with anything, including other modules, this drastically reduces code duplication and lets you manage the code on a higher level (while still seeing how does it correspond to bits and wires).

laydn 5y ago
It's not that we have a low standard, it's that we are bound by the full suite of tools that are provided to us in order to achieve our design objective. When I am close to tapeout and I am moving a single gate across a flip flop in order to extract the final few Mhz out of the design, and my formal equivalence checker only understands Verilog, I will have to use Verilog. I suppose my benchmark in assessing the capabilities of this -or any- language and its ecosystem is the following : Can you use Clash in the design of a reasonably complex chip from scratch (HDL to tapeout)?

exdsq 5y ago

I'm looking at it through another lens - a way to improve my intermediate haskell and learn about HDL. Maybe they're pushing for commercial use but there are alternative reasons to be interested in this too!

qwerty456127 5y ago

The purpose of making anything Haskell-based probably is making it mathematically verifiable. Isn't it?