Micro-ops often have more bits than the ISA they're implementing, so you'd pay a program-size penalty. Moreover, Intel (and I assume AMD), will take a sequence

Micro-ops often have more bits than the ISA they're implementing, so you'd pay a program-size penalty. Moreover, Intel (and I assume AMD), will take a sequence of micro ops corresponding to a sequence of "instructions" and optimize the micro-op sequence based on dynamic usage, together with "undo" for when the usage assumptions are wrong.