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It's JIT support for the OpenPOWER architecture, which is interesting, but as far as I can tell isn't exactly in wide use right now. At least not where you migh

It's JIT support for the OpenPOWER architecture, which is interesting, but as far as I can tell isn't exactly in wide use right now. At least not where you might need Firefox. https://openpowerfoundation.org/ https://openpowerfoundation.org/

detaro 5y ago
EDITED: derp, confused: There are POWER Workstations from Raptor Computing Systems (https://www.raptorcs.com/ https://www.raptorcs.com/). Talospace are POWER enthusiasts. Thanks amock for the correction.
- throwaway894345 5y ago
  How do POWER CPUs compare with ARM, x86, etc?
  - boibombeiro 5y ago
    They are target at datacenters. The last iteration has hardware support to decimal floating point, flexible IO (DDR3, DDR4, DDR5. GDDR6, HBM, PCI5, nvlink), Cores with SMT8, Tbps intra chip network, etc Can change the endianess at run time. Their new cache architecture is very unusual. A CPU can use the cache from another chip. Data is stored encrypted.
    - falcor84 5y ago
      If the system can change the endianess at any time, does that mean that we should only be using palindromic data? Or is it that we should aim to make everything polyglotic such that both directions have valid but distinct interpretations? ;)
      - jazzyjackson 5y ago
        you joke but I learned at a talk comparing genetics to TCP networking (at HOPE, maybe 2014 or 2016, cant find it on the website atm) that DNA is encoded such that it expresses different proteins depending on which direction it is read, might be something to learn from
    - bawolff 5y ago
      Interesting. What would the benefit be of changing endianess at runtime? From an efficiency perspective does that mean the chip has to do both so worst of both worlds? [I dont know much about the world of cpu design, these might be stupid questions]
      - cmrdporcupine 5y ago
        It's more something you'd do at boot, if you had to select between an OS built for one or another. The POWER ISA was used in PowerPC which was used for the successors of a few 68k machines (most famously the Macintosh) and in that case the OS was built for big-endian. So having big-endian support was key there.
        classichasclass 5y ago
        IBM i and AIX still run big, in fact. Important for IBM's institutional customers. As for endian shifts, technically every OpenPOWER chip goes big for every OPAL call into the low-level HAL, even if the OS is little. The overhead is minimal. I can't think of much application use for that, though (per-page endianness which some PowerPCs supported is much more useful).
      - boibombeiro 5y ago
        Network application. The CPU probably works on just one endianess and convert the data format when reading from memory. The overhead is on kepping track when to do it. But Im speculating, havent looked into this.
    - usrusr 5y ago
      Sounds like an architecture full of features you'd like to avoid when you want to run on battery, run as many of them in a datacenter of a given heat dissipation capacity or simply when you're big enough to tailor a CPU design to your needs because you can buy from a chip manufacturing as a service company. Truly an architecture for a different century.
      - boibombeiro 5y ago
        Most company can't afford to make custom chip at 7 nm. The IBM Power is one implementation of the Power ISA. The chips used on the mars rovers and nintendo Wii as ppc as well.
    - floatboth 5y ago
      armv8 defines the registers for changing endianness too :) https://developer.arm.com/documentation/den0024/a/ARMv8-Registers/Endianness https://developer.arm.com/documentation/den0024/a/ARMv8-Regi... Cortex cores at least do support switching endianness for data in userspace (SCTLR_EL1.E0E)
      - my123 5y ago
        > Cortex cores at least do support switching endianness for data in userspace (SCTLR_EL1.E0E) Yeah, Cortex and NVIDIA cores do (and probably quite some others). However, Apple-designed recent cores don’t implement big endian support at all.
- amock 5y ago
  The man behind talospace.com doesn't make workstations, he has one from https://raptorcs.com/ https://raptorcs.com/. He's a PowerPC enthusiast.
- thuccess129 5y ago
  Isn't a better allocation of scarce engineering resources on the POWER platform to implement a RDP client to x86 commodity desktop environment for the commercial consumer experience on the web with the benefit of offsetting and isolating potential security breach to that environment? Has anyone made the POWER CPU a raw node for crunching styled on the Plan 9 idea of cpu% ?
josephg 5y ago
I'm missing a lot of context. Can someone explain why POWER9 is interesting? Is OpenPOWER trying to compete with RISC-V? Whats the benefit compared to modern ARM or x86_64 silicon & ISAs?
- spijdar 5y ago
  POWER9 is interesting (compared to RISC-V) because, right now, you can buy up to a 24 core, SMT4 system (96 threads), running dual CPU sockets if you like, and supporting up to 1 TB of memory per socket, with a maximum boosted clock speed of 3.8 GHz. All this with fully open firmware, and an open ISA (as of the last couple years). The CPU implementation itself is not open, but all firmware and procedures for initializing the CPU are open. For people interested in that sort of thing, it's appealing as a practical computer with a full PCIe implementation with actually decent performance, compared to essentially every other open source platform.
  - classichasclass 5y ago
    In fact, you could get a Talos II with dual 22-core CPUs for a whopping 176 threads, even. Raptor has them in stock.
    - whatshisface 5y ago
      Are the prices of these CPUs comparable to x86 CPUs with similar performance?
      - AnthonyMouse 5y ago
        In a sense they are, because with those core counts, you're comparing to Epyc and Xeon, which are similarly very expensive. What they're really missing is a midrange product for a midrange price. I can't blame them for avoiding the low end, but can't I get anything for less than $2000?
        deleted 5y ago

detaro 5y ago

EDITED: derp, confused: There are POWER Workstations from Raptor Computing Systems (https://www.raptorcs.com/ https://www.raptorcs.com/). Talospace are POWER enthusiasts. Thanks amock for the correction.

throwaway894345 5y ago
How do POWER CPUs compare with ARM, x86, etc?
- boibombeiro 5y ago
  They are target at datacenters. The last iteration has hardware support to decimal floating point, flexible IO (DDR3, DDR4, DDR5. GDDR6, HBM, PCI5, nvlink), Cores with SMT8, Tbps intra chip network, etc Can change the endianess at run time. Their new cache architecture is very unusual. A CPU can use the cache from another chip. Data is stored encrypted.
  - falcor84 5y ago
    If the system can change the endianess at any time, does that mean that we should only be using palindromic data? Or is it that we should aim to make everything polyglotic such that both directions have valid but distinct interpretations? ;)
    - jazzyjackson 5y ago
      you joke but I learned at a talk comparing genetics to TCP networking (at HOPE, maybe 2014 or 2016, cant find it on the website atm) that DNA is encoded such that it expresses different proteins depending on which direction it is read, might be something to learn from
  - bawolff 5y ago
    Interesting. What would the benefit be of changing endianess at runtime? From an efficiency perspective does that mean the chip has to do both so worst of both worlds? [I dont know much about the world of cpu design, these might be stupid questions]
    - cmrdporcupine 5y ago
      It's more something you'd do at boot, if you had to select between an OS built for one or another. The POWER ISA was used in PowerPC which was used for the successors of a few 68k machines (most famously the Macintosh) and in that case the OS was built for big-endian. So having big-endian support was key there.
      - classichasclass 5y ago
        IBM i and AIX still run big, in fact. Important for IBM's institutional customers. As for endian shifts, technically every OpenPOWER chip goes big for every OPAL call into the low-level HAL, even if the OS is little. The overhead is minimal. I can't think of much application use for that, though (per-page endianness which some PowerPCs supported is much more useful).
    - boibombeiro 5y ago
      Network application. The CPU probably works on just one endianess and convert the data format when reading from memory. The overhead is on kepping track when to do it. But Im speculating, havent looked into this.
  - usrusr 5y ago
    Sounds like an architecture full of features you'd like to avoid when you want to run on battery, run as many of them in a datacenter of a given heat dissipation capacity or simply when you're big enough to tailor a CPU design to your needs because you can buy from a chip manufacturing as a service company. Truly an architecture for a different century.
    - boibombeiro 5y ago
      Most company can't afford to make custom chip at 7 nm. The IBM Power is one implementation of the Power ISA. The chips used on the mars rovers and nintendo Wii as ppc as well.
  - floatboth 5y ago
    armv8 defines the registers for changing endianness too :) https://developer.arm.com/documentation/den0024/a/ARMv8-Registers/Endianness https://developer.arm.com/documentation/den0024/a/ARMv8-Regi... Cortex cores at least do support switching endianness for data in userspace (SCTLR_EL1.E0E)
    - my123 5y ago
      > Cortex cores at least do support switching endianness for data in userspace (SCTLR_EL1.E0E) Yeah, Cortex and NVIDIA cores do (and probably quite some others). However, Apple-designed recent cores don’t implement big endian support at all.
amock 5y ago
The man behind talospace.com doesn't make workstations, he has one from https://raptorcs.com/ https://raptorcs.com/. He's a PowerPC enthusiast.
thuccess129 5y ago
Isn't a better allocation of scarce engineering resources on the POWER platform to implement a RDP client to x86 commodity desktop environment for the commercial consumer experience on the web with the benefit of offsetting and isolating potential security breach to that environment? Has anyone made the POWER CPU a raw node for crunching styled on the Plan 9 idea of cpu% ?

josephg 5y ago

I'm missing a lot of context. Can someone explain why POWER9 is interesting? Is OpenPOWER trying to compete with RISC-V? Whats the benefit compared to modern ARM or x86_64 silicon & ISAs?

spijdar 5y ago
POWER9 is interesting (compared to RISC-V) because, right now, you can buy up to a 24 core, SMT4 system (96 threads), running dual CPU sockets if you like, and supporting up to 1 TB of memory per socket, with a maximum boosted clock speed of 3.8 GHz. All this with fully open firmware, and an open ISA (as of the last couple years). The CPU implementation itself is not open, but all firmware and procedures for initializing the CPU are open. For people interested in that sort of thing, it's appealing as a practical computer with a full PCIe implementation with actually decent performance, compared to essentially every other open source platform.
- classichasclass 5y ago
  In fact, you could get a Talos II with dual 22-core CPUs for a whopping 176 threads, even. Raptor has them in stock.
  - whatshisface 5y ago
    Are the prices of these CPUs comparable to x86 CPUs with similar performance?
    - AnthonyMouse 5y ago
      In a sense they are, because with those core counts, you're comparing to Epyc and Xeon, which are similarly very expensive. What they're really missing is a midrange product for a midrange price. I can't blame them for avoiding the low end, but can't I get anything for less than $2000?
      - deleted 5y ago