3 ms·
Oh my god, did you just discredit the entire field of EDA place & route in just one sentence? This is not your usual 20MHz bus. These are signals that switch at
by AshamedCaptain 5y ago
Oh my god, did you just discredit the entire field of EDA place & route in just one sentence? This is not your usual 20MHz bus. These are signals that switch at 2, 3, 4 GHz, and there are a shitton of effects that get in the way and limit how fast you can toggle a (longer) wire. Or at least significantly alter the power vs latency vs speed vs noise tradeoffs.
(and no, I most certainly did not buy into apple marketing, since I'm pointing that as a negative)
- rasz 5y agoDid you miss the part where Apple is clocking those chips at same speeds as normal DDR4? Closer placement did not result in lower latency nor higher speeds. Apple M1 is same situation as RPI foundation using POP ram. Requires fewer pcb layers, simplifies layout, lowers cost and as a bonus gives assured future sales due to forced obsolescence. I didnt dismiss anything, I simply know physics and have some experience in high speed layout.
- AshamedCaptain 5y agoI can understand the claim the M1 has the same timings as off-the-shelf DDR4 (thought this was a nice way to explain the apparent increases in memory bandwidth shown in benchmarks), but here you are dismissing the concept of HBM entirely.
- rasz 5y agoAfaik M1s dont use HBM (which is 1024bit per chip and are their own thing), but ordinary POP ram like RPI. Anything up to 512bits is just cost cutting. Look at Xbox - no problem fanning out 320bit bus in addition to pcie lanes, same for hiend GPUs. 4096bit is where you can claim someone actually uses HBM for performance, like on Radeon R9 Nano/Fury.
- deleted 5y ago[deleted]