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The Soviet 1801VM3 Enhanced LSI-11 Processor
- ginko 5y agoThis article is really missing some context on when this processor came out and how it compares technology-wise with other processors of its time.
- rented_mule 5y agoIt's Soviet, so <= 1991 (and there are references to 1991 and post-1991 updates). There's a link at the top of the article to a similar article about this chip's predecessor, "developed in 1982". It appears they implement the PDP-11 instruction set. The western-designed contemporaries of the chip in the article would roughly be Intel 80386/80486 and Motorola 68030/68040. Some of the details (e.g., clock speed, address space, transistor count, package, etc.) look closer to 8088 and 68000. So it appears to be 2-3 generations behind Intel and Motorola.
- jacquesm 5y agoThe PDP 11 was a 1970's machine. So more like 20 years behind.
- thriftwy 5y agoThese were meant for simple PCs aimed at students. Yamaha MSX and Sinclair clones used similarly dated Z80 way into 90s as well. If you think late soviet CPUs are behind, wait until you see late soviet cars
- p_l 5y agoPDP-11 was a bit heavier design, and while it started in 1970s, it was evolving and built with newer designs till 1990s at least (I think last manufactured units were late 1990s). 1801 line is curious in how it was single chip while the "original" LSI-11 was 2 chip at the time. Meanwhile 1801 was small enough that there are pocket calculators built on it, that a sufficiently deranged EE student can turn into Unix machine.
- jacquesm 5y agoI lived in Poland at the time the wall came down and I'm quite familiar with (and really like some) Soviet cars.
- p_l 5y agoThe specific variant that it was compatible with was still relevant, sold and manufactured design at the time of the introduction (ca. 1985? maybe a bit earlier). It was a very capable CPU for its weight class, and actually more packed than Digital's offering at the time - most LSI-11 at the time required two separate chips minimum, and didn't have 1801VM3's later "MCU" variants. The reason for it was that it wasn't designed as PDP-11 clone - it was own design, which at the last moment got modified to run LSI-11 instruction set and support QBus, due to orders from on-high to standardize on PDP-11 compatibles in the segment it was made for.
- guenthert 5y agoWasn't it originally meant to be used my the armed forces? I think the '85 introduction to the general market was only after the original users considered it not competitive anymore.
- p_l 5y agoNope. It was originally meant to power industrial machinery, and in fact some very early chips that used the in-house instruction set were made and ended up AFAIK in some fabrication machines (lathes, mills, etc). Afterwards it was a welcome upgrade for PDP-11 based lines, including military spec models, where reliability was more important than pure speed.
- retrac 5y agoThe PDP-11 wasn't crammed into a LSI design on five chips until 1975 with the F-11 that implemented it fast on two chips coming in 1979. Performance-wise the 1801 is comparable to the F-11. It seems to have been produced c. 84 onward. About five years behind. Which is typical throughout the Soviet era. TTL became common c. 1970 about five years after the West. The first 8080 clones came out around 1980 to 81 some five to six years after Intel. Robotron in the DDR had working copies in '89 of the Microvax chipset from '85 as they rushed to copy 32 bit designs - only four years. The cutting edge for the semiconductor industry in the East was typically two generations and five years behind, pretty consistently, from what I can tell.
- rbanffy 5y agoIt saddens me that instead of PDP-11 we ended up with x86. OTOH, it’s hard to imagine how inelegant the PDP-11 would have become if it evolved the same way the 8086 turned into Golden Cove.
- nine_k 5y ago8086 was inelegant from the beginning. PDP-11 was elegant. It could have had a better chance. OTOH PDP-11 was very heavily invested in operating directly in RAM; a lot of commands could operate on RAM, and MOV could even have two indirect RAM operands (registers have address of addresses of the operands). Considering the memory wall we've started to hit like 20 years ago, such an architecture would have a rather hard time competing with RISC.
- addaon 5y agoWould it, or would we have had a convention in later versions that the low N words of the memory map actually refer to registers? This would not resolve the instruction size issues of a memory-to-memory encoding, but it would give two paths to register file growth (growing the number of architectural registers by increasing N as the architecture evolves; and the usual register renaming games), both of which would be software-compatible with previous versions. Having eight named registers and 256 -- or 4096 -- numbered fast registers, plus renaming on top of that, actually seems like an interesting path.