3 ms·
I’m speculating but when I’ve seen it in the past it was for handling higher current. In this case I’m wondering if it’s used to maintain better control of the
by FPGAhacker 5y ago
I’m speculating but when I’ve seen it in the past it was for handling higher current.
In this case I’m wondering if it’s used to maintain better control of the voltage gradient on a pad.
- ejiblabahaba 5y agoSometimes it's to handle higher currents, other times it's to reduce the bond wire inductance and improve the high-frequency response. For power pins it can be both. Especially for a multi-chip module with some digital circuitry, there's potential for high-frequency digital transients that need nearby decoupling capacitors through low-inductance loops, or the transistor switching noise can pollute other copackaged circuit supplies; amplifiers also benefit from lower inductance on the supply lines since it stabilizes the frequency response at higher offsets beyond the loop bandwidth of any integrated supply regulation, current sources, bandgap references etc. So you're essentially correct, it's about voltage gradients, but probably at higher frequency.