5 ms·
For any Renesas folks reading this, you should consider throwing in with the open-source Icestorm toolchain. Icestorm brought a ton of exposure to Lattice's lo
by nrclark 5y ago
For any Renesas folks reading this, you should consider throwing in with the open-source Icestorm toolchain.
Icestorm brought a ton of exposure to Lattice's low-end FPGAs, and that was with no official support from Lattice. Renesas could have that too. If you have to spend money on software anyways, why not spend it improving the overall ecosystem? The marketing impact could be huge for getting the word out to designers like me that hate the big-names' toolchains.
- detaro 5y agoThey use yosys apparently.
- nrclark 5y agoNice! What about place/route?
- detaro 5y agoNot sure, just saw a screenshot of their tooling somewhere with yosys output showing, didn't have time to poke around myself yet.
- Rochus 5y agohttps://hdl.github.io/awesome/items/vpr/ https://hdl.github.io/awesome/items/vpr/ https://github.com/YosysHQ/nextpnr https://github.com/YosysHQ/nextpnr
- moring 5y agoThere is no mention on those pages on whether Renesas uses those tools.
- monocasa 5y agoHere's hoping they open source their modifications.
- xvilka 5y agoIceStorm is a part of SymbiFlow [1] now. [1] https://symbiflow.github.io/ https://symbiflow.github.io/
- Rochus 5y agoThere is even a free/open-source Verilog IDE which could be used and which works well with Yosys: https://github.com/rochus-keller/VerilogCreator https://github.com/rochus-keller/VerilogCreator
- blikdak 5y agoI just ran a synthesis of their include demo Blinky and it ended with: End of script. Logfile hash: 00b456ea46, CPU: user 3.19s system 0.13s Yosys 0.10.0 (git sha1 a743417f0, clang 12.0.0 -fPIC -Os) Time spent: 63% 17x read_verilog (2 sec), 6% 1x synth_xilinx (0 sec), ... 11/21/21 12:03 PM > Finished running Yosys with status: 0 (!!!)