For the simple ops used in these particular algorithms, it should be possible to use SIMD to saturate the pipeline, getting high throughput for the same latency

For the simple ops used in these particular algorithms, it should be possible to use SIMD to saturate the pipeline, getting high throughput for the same latency, assuming SIMD is part of the ISA. Cache misses wouldn't be a factor in comparing hash algorithms, as the memory layout is a feature of the hash input, and hash state would typically either be in register or in cache