3 ms·
Worth pointing out for bystanders that in superscalar, pipelined processors the number of instructions has very little bearing over whether something is faster
by cafxx 5y ago
Worth pointing out for bystanders that in superscalar, pipelined processors the number of instructions has very little bearing over whether something is faster or slower (unless we are talking about differences of many orders of magnitude in the number of instructions). This applies even if we are not talking about instructions that deal with memory or I/O.
- h0l0cube 5y agoFor the simple ops used in these particular algorithms, it should be possible to use SIMD to saturate the pipeline, getting high throughput for the same latency, assuming SIMD is part of the ISA. Cache misses wouldn't be a factor in comparing hash algorithms, as the memory layout is a feature of the hash input, and hash state would typically either be in register or in cache
- vardump 5y agoSure. But even if the CPU doesn't interleave them in reorder buffer, you can do it. At least as long as the dependency chain isn't too long. Even if the dependency chain is too long for the CPU (or you) to split it, the CPU can always run hyperthread while waiting.