I think the point the parent is making is that this ECC is already fixing errors. There's no redundancy because the redundancy is already consumed by the defec

I think the point the parent is making is that this ECC is already fixing errors. There's no redundancy because the redundancy is already consumed by the defective cells in the chip. Any additional flips such as through rowhammer have no extra redundancy to fall back on in the general case with DDR5's built-in ECC.