2 ms·
I guess another plus for DDR5 which has some ECC built in to including in the non-ECC versions.
by sroussey 5y ago
I guess another plus for DDR5 which has some ECC built in to including in the non-ECC versions.
- temac 5y agoThe internal ECC in basic DDR5 is intended to provide a reliability just good enough to be at the level of DDR4 without ECC (or maybe slightly above, but probably not a lot?), and likely the error rate would just be crazy high without any DDR5 internal "ECC" at all -- even without a rowhammer pattern or cosmic rays, etc. I not sure it will help against rowhammer (and variants)?
- egberts1 5y agoOriginal author already said DDR5 ECC, once mapped, will too suffer SPECTRE.
- AaronFriel 5y agoSPECTRE is a CPU vulnerability in the speculative execution that modern processors perform to create a side channel to leak data through. Could you elaborate on what you mean by DDR5 "suffering" from SPECTRE? I believe that vulnerability is memory technology agnostic and theoretically would work if you could boot a CPU absent any memory at all, as the leaks occur through CPU caches.
- egberts1 5y agoCPU? More like memory controller and their capacitance banks.
- sroussey 5y agoAgreed, though did the spec for ddr5 finalize after row-hammer? Seems like an opportunity to adjust for attacks. They should do another set of tests on DDR5 and compare to DDR4.
- rkunde 5y agoAn improved rowhammer mitigation called Refresh Management (RFM) is part of DDR5 spec, but it’s optional and requires host OS support from what I’ve read.