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> DDR4 pages ("rows") are 8kiB Wait, are the underlying hardware access size for memory bigger than the default Linux page size (4kb)? Wouldn't that introduce
by yxhuvud 5y ago
> DDR4 pages ("rows") are 8kiB
Wait, are the underlying hardware access size for memory bigger than the default Linux page size (4kb)? Wouldn't that introduce needless inefficiencies?
Can false sharing happen between different pages if they happen to be in the same row?
- namibj 5y agoWhat you don't want is things accessed together residing in different rows of the same bank. Things being on the same row is a good thing.
- yxhuvud 5y agoEven for false sharing? That is, the problem when two unrelated atomics are allocated in the same page but accessed frequently from different threads, causing the memory to be thrashing between two different L1 cache lines.
- dragontamer 5y agoNot really. Pages are about virtual memory and not about physical memory. In practice, the only thing DDR4 banks do is make prefetching an important strategy, thus making sequential performance for DDR4 incredible. A fact already known to high performance programmers. Accessing byte 65 after byte 64 is much more efficient than accessing byte 9001.
- rasz 5y agoIts internal implementation detail, invisible to the CPU. https://faculty-web.msoe.edu/johnsontimoj/EE4980/files4980/memory_sdram_operation.pdf https://faculty-web.msoe.edu/johnsontimoj/EE4980/files4980/m... diagrams on pages 4-7.