DDR4 DIMMs have (almost?) exclusively 8kiB pages. If you have 2 channels with interleaving, like AFAIK the default on all current x86 desktop platforms, you get

DDR4 DIMMs have (almost?) exclusively 8kiB pages. If you have 2 channels with interleaving, like AFAIK the default on all current x86 desktop platforms, you get the same 16kiB effective page size as the typical[0] TLB compressing (which smashes the 4 4kiB pagetable entries in a cacheline worth of lowest-level pagetable into a single virtual 16kiB TLB entry if they have the same attributes and look exactly as a smashed 16kiB page table entry would look like (alignment, contiguous, etc.)). [0]: Zen3 does it for sure, but I think I also saw it somewhere else.