4 ms·
It's not software that's the problem, it's the hardware that still doesn't perform at the level that was expected when it was under development. This is becaus
by bcrl 5y ago
It's not software that's the problem, it's the hardware that still doesn't perform at the level that was expected when it was under development. This is because of the fact that the 3DXPoint / Optane cells have higher than planned errors rates which require a controller much like flash does to perform error correction and wear leveling. This makes it impossible to provide the same latency as DRAM (the original goal), and pushes power requirements for the DIMM form factor up since each DIMM has to have its own controller for the 3DXPoint memory. So now you have most of the problems of flash without cells that store multiple bits (as in TLC/QLC flash) or the 3d layering that flash vendors now use.
Suffice it to say that it was promising while it was under development, but Intel neglected to factor in just how much flash vendors would improve performance and reduce cost per bit.
- simcop2387 5y agoI wonder how that compares with ddr5 which has a controller and new power systems for similar reasons then. Combined with the upcoming CXL bus stuff it makes me womder if it'll happen it's just the interface wasn't ready yet
- wmf 5y agoDDR5 does not have a controller on the DIMM; it's nothing like the complexity of Optane DIMMs. I agree that CXL seems like a better fit for Optane than a memory bus.
- simcop2387 5y agoah yes, it's just a clocking driver. the ecc requirements are into the ram chips themselves. i had misremembered. https://www.rambus.com/memory-and-interfaces/server-dimm-chipsets/ddr5-dimm-chipset/ https://www.rambus.com/memory-and-interfaces/server-dimm-chi...
- bcrl 5y agoIt's more a question of Amdahl's law: the introduction of SSDs brought I/O latencies from the 5 to 10 milliseconds of HDDs down to tens to hundreds of microseconds. Going from tens of microseconds to 100-200 nanoseconds is much less of an improvement for most general purpose workloads.