I find VHDL unpleasant (and Verilog only slightly less so, even if it's the worse language) but the hard part for someone with a programming background isn't th

I find VHDL unpleasant (and Verilog only slightly less so, even if it's the worse language) but the hard part for someone with a programming background isn't the language per se, it's learning how to design digital logic, which is very different from writing software.