My understanding is that for general purpose registers, register renaming and other hazard-avoiding optimisations means that the register file is significantly

My understanding is that for general purpose registers, register renaming and other hazard-avoiding optimisations means that the register file is significantly larger than the total of (register width * number of registers). Do the SIMD units have similar register duplications? If so, reducing the duplication count would do pretty much that (Reducing the area at the cost of lower performance). Even if not, the large general purpose register duplication count likely means that the SIMD registers are actually a lower proportion of the register file on chip than the register width would imply, making it less of a saving. But generally I agree, I'm much more interested in the extra instruction vocabulary and things like masking lanes than the increased register width. I also wonder at what point the cut off of when a use case would be worth pushing to a more dedicated accelerator (like a dsp or gpu).