> Meanwhile we're stuck with SIMD now instead of MIMD… What about multi-core/multi-threading combined with massively out of order CPUs? Intel and AMD’s chips h

> Meanwhile we're stuck with SIMD now instead of MIMD… What about multi-core/multi-threading combined with massively out of order CPUs? Intel and AMD’s chips have a dozen or so execution ports. So you can have your PADD running on one port, and a PMUL on another. It just happens all being the scenes. Intel tried a VLIW architecture with Itanium, but it was a flop for a variety of reasons. One of which was the lack of “sufficiently smart compilers”. There’s also the benefit to all the nuances of execution being in hardware: programs benefit from new CPUs without having to be recompiled. It has a much more intimate knowledge of how things are going than the software does (or even the compiler).